The present invention relates generally to processing systems and in particular the present invention relates to a memory interface which allows interchangablity of multiple memory devices.
A memory device is the place where a computer processor holds current programs and data that are in use, and, because of the demands made by increasingly powerful software, system memory requirements have been accelerating at an alarming pace over the last few years. The result is that modern computers have significantly more memory than the first computers of the early 1980s, and this has had an effect on development of processor architectures. Storing and retrieving data from a large block of memory is more time-consuming than from a small block. With a large amount of memory, the difference in time between a register access and a memory access is very great, and this has resulted in extra layers of xe2x80x98cachexe2x80x99 memory in the storage hierarchy. When it comes to access speed, processors are currently outstripping memory chips by an ever-increasing margin.
System memory can comprise different types of memory. Synchronous dynamic random access memory (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional memory. The SDRAM synchronizes itself with a central processing unit""s (CPU) bus and is capable of running at speeds of about 100 MHZ, about three times faster than conventional fast page mode (FPM) DRAM, and about twice as fast as extended data output (EDO) DRAM and burst EDO DRAM. SDRAM, therefore, is replacing EDO DRAM in many newer computers
Today""s fastest processing systems use CPU buses running at, or in excess of, 100 MHZ, so SDRAM can marginally maintain the bus speed. Future processing systems, however, are expected to have CPU buses running at 200 MHZ or faster. SDRAM is not expected to support these high speeds which is why new memory technologies are being developed.
RAMBUS DRAM (RDRAM) is a type of memory developed by RAMBUS, Inc., Mountain View, Calif. It is anticipated that RDRAM can transfer data at up to 600 MHZ. RDRAM is being used in place of video RAM (VRAM) in some graphics accelerator boards, but it is not expected to be used for the main memory of processing systems until 1999.
Both the cost and availability of RDRAM creates a barrier to widespread use of the memory in processing systems. Thus, processors developed which are designed to communicate with RDRAM may not experience widespread acceptance until RDRAM is economically available. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an apparatus and method which allows a processing system, originally designed to use RDRAM, to use more economical memory devices.
In one embodiment, a processing system comprises a memory controller adapted to communicate using a packet based RDRAM protocol, a memory module comprising SDRAM devices, and an interface device located with the memory controller such that the interface device is not located on the memory module. The interface device translates packet based RDRAM protocol command and data signals from the memory controller into an SDRAM protocol, and the interface device translates data signals received from the memory module into packet based RDRAM protocol data.
In another embodiment, a processing system comprises a memory controller adapted to communicate using a packet based RDRAM protocol, a memory module comprising SDRAM devices, the memory module is located in a memory socket, and an interface device located between the memory controller and the memory socket. The interface device translates packet based RDRAM protocol command and data signals from the memory controller into an SDRAM protocol, and the interface device translates data signals received from the memory module into packet based RDRAM protocol data.
In still another embodiment, a processing system comprises a memory controller adapted to communicate using a packet based RDRAM protocol, and a memory module comprising SDRAM devices. The memory module is located in a memory socket. An interface device is located between the memory controller and the memory socket. The interface device translates packet based RDRAM protocol command and data signals from the memory controller into an SDRAM protocol. The interface device comprises a write demultiplex circuit for converting data received on N data lines from the memory controller to Mxc3x97N data lines, a read multiplex circuit converting received on the Mxc3x97N data lines from the memory module to the N data lines, and a command disassembler for converting packet based commands from the memory controller into row/column based commands.